{"id":13611,"date":"2023-01-16T10:46:53","date_gmt":"2023-01-16T05:16:53","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=13611"},"modified":"2023-08-19T15:21:26","modified_gmt":"2023-08-19T09:51:26","slug":"microcontroller-embedded-c-programming-lecture-161-bit-field-structure-for-gpiox_odr","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/microcontroller-embedded-c-programming-lecture-161-bit-field-structure-for-gpiox_odr\/","title":{"rendered":"Microcontroller Embedded C Programming Lecture 161| Bit-field structure for GPIOx_ODR"},"content":{"rendered":"
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Bit-field structure for GPIOx_ODR<\/span><\/strong><\/h1>\n
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A GPIOx_ODR (GPIO Output Data Register) is a register used in microcontrollers or systems-on-chip (SoCs) to control the output state of the GPIO (General Purpose Input\/Output) pins. <\/span><\/p>\n

A bit-field structure for the GPIOx_ODR register defines the individual bits within the register and their corresponding functions. The exact structure of the register can vary depending on the specific microcontroller or SoC architecture.<\/span><\/p>\n

I created typedef structures for the GPIO_ODR register and also for the GPIO_MODE register.<\/span><\/p>\n

typedef struct<\/span>\r\n{\r\n    uint32_t<\/span> pin_0    :1;\r\n    uint32_t<\/span> pin_1    :1;\r\n    uint32_t<\/span> pin_2    :1;\r\n    uint32_t<\/span> pin_3    :1;\r\n    uint32_t<\/span> pin_4    :1;\r\n    uint32_t<\/span> pin_5    :1;\r\n    uint32_t<\/span> pin_6    :1;\r\n    uint32_t<\/span> pin_7    :1;\r\n    uint32_t<\/span> pin_8    :1;\r\n    uint32_t<\/span> pin_9    :1;\r\n    uint32_t<\/span> pin_10   :1;\r\n    uint32_t<\/span> pin_11   :1;\r\n    uint32_t<\/span> pin_12   :1;\r\n    uint32_t<\/span> pin_13   :1;\r\n    uint32_t<\/span> pin_14   :1;\r\n    uint32_t<\/span> pin_15   :1;\r\n    uint32_t<\/span> reserved :16;\r\n}GPIOx_ODR_t<\/span>;<\/pre>\n
typedef struct for the GPIOx_ODR register<\/span><\/p>\n
In this example, each bit in the register corresponds to a specific GPIO pin, numbered from 0 to 15. The pin_0<\/code> bit controls the output state of GPIO Pin 0, Pin_1<\/code> bit controls GPIO Pin 1, and so on. The structure also includes reserved bits, which are typically used for alignment or future use.<\/span><\/p>\n
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typedef struct<\/span>\r\n{\r\n    uint32_t<\/span> pin_0  :2;\r\n    uint32_t<\/span> pin_1  :2;\r\n    uint32_t<\/span> pin_2  :2;\r\n    uint32_t<\/span> pin_3  :2;\r\n    uint32_t<\/span> pin_4  :2;\r\n    uint32_t<\/span> pin_5  :2;\r\n    uint32_t<\/span> pin_6  :2;\r\n    uint32_t<\/span> pin_7  :2;\r\n    uint32_t<\/span> pin_8  :2;\r\n    uint32_t<\/span> pin_9  :2;\r\n    uint32_t<\/span> pin_10 :2;\r\n    uint32_t<\/span> pin_11 :2;\r\n    uint32_t<\/span> pin_12 :2;\r\n    uint32_t<\/span> pin_13 :2;\r\n    uint32_t<\/span> pin_14 :2;\r\n    uint32_t<\/span> pin_15 :2;\r\n}GPIOx_MODE_t<\/span>;<\/pre>\n
typedef struct for the GPIOx_MODE register<\/span><\/p>\n
Here I used the name GPIOx because the same structure I can use with any GPIO peripheral. It need not be  GPIOD, GPIOA, or GPIOB. So, this is a generic structure. Because it can be used with mode to register of any GPIO peripheral.<\/span> <\/span><\/span><\/p>\n
And  pin_0, pin_1, pin_2, pin_15, and so on, these are the member elements. So, here you can even use pin mode 0, or pin mode 1, like that. I just used the names pin_0, and pin_1, like that.<\/span><\/p>\n
And for the GPIOx_ODR, you can see that(Figure 1) only 15-bit positions are valid and the rest are reserved. So, that’s the reason 16-bit positions are reserved.<\/span><\/p>\n
In the following article, let’s see what to do with these typedef structures. So, we have learn how to configure the peripheral registers using these typedef structures. <\/span><\/p>\n
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FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n
Click here: <\/span><\/span>https:\/\/fastbitlab.com\/course1<\/span><\/a><\/span><\/p>\n
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  Bit-field structure for GPIOx_ODR   A GPIOx_ODR (GPIO Output Data Register) is a register used in microcontrollers or systems-on-chip (SoCs) to control the output state of the GPIO (General Purpose Input\/Output) pins. A bit-field structure for the GPIOx_ODR register defines the individual bits within the register and their corresponding functions. The exact structure of […]<\/p>\n","protected":false},"author":1,"featured_media":13614,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"enable","ocean_disable_heading":"default","ocean_post_title":"Bit-field structure for GPIOx_ODR","ocean_post_subheading":"","ocean_post_title_style":"solid-color","ocean_post_title_background_color":"#005da0","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[16],"class_list":["post-13611","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","tag-microcontroller-embedded-c-programming","entry","has-media"],"yoast_head":"\nBit-Field Structure for GPIOx_ODR Register: Control GPIO Output State<\/title>\n<meta name=\"description\" content=\"Bit-field structure for GPIOx_ODR. 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