{"id":14428,"date":"2023-04-19T10:33:42","date_gmt":"2023-04-19T05:03:42","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=14428"},"modified":"2023-09-07T12:42:53","modified_gmt":"2023-09-07T07:12:53","slug":"stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-17-setting-up-main-system-clock-code-implementation-part-1","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-17-setting-up-main-system-clock-code-implementation-part-1\/","title":{"rendered":"STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 17| Setting up main system clock code implementation part-1"},"content":{"rendered":"
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Setting up main system clock code implementation part-1<\/strong><\/span><\/h1>\n
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In this article, we will begin creating the main clock code for our application. Having an accurate clock is essential for many applications and devices, and it’s no different in our case. The timekeeping module of our application is the backbone of the system, and we need to make sure that it is reliable and accurate.<\/span><\/p>\n

The project has two header files: <\/span>reg_util.h<\/b> and <\/span>stm32f429xx.h<\/b>. These files contain essential information that we need to access the microcontroller’s registers and set up the clock.<\/span><\/span><\/p>\n

The <\/span>reg_util.h<\/b> file contains some macros that we can use to configure the microcontroller’s registers. These macros are displayed in below. They make our code more readable and understandable by providing us with a shorthand notation for accessing the registers.<\/span><\/span><\/p>\n

#ifndef<\/span> REG_UTIL_H_<\/span>\r\n#define<\/span> REG_UTIL_H_<\/span>\r\n\r\n\/* Register bit manipulation macros *\/<\/span>\r\n\r\n#define<\/span> REG_WRITE<\/span>(reg, val) ((reg) = (val))\r\n#define<\/span> REG_READ<\/span>(reg) ((reg))\r\n#define<\/span> REG_SET_BIT<\/span>(reg,pos) ((reg) |= (1U << (pos)))\r\n#define<\/span> REG_CLR_BIT<\/span>(reg,pos) ((reg) &= ~(1U << (pos)))\r\n#define<\/span> REG_READ_BIT<\/span>(reg,pos) ((reg) & (1U << (pos)))\r\n#define<\/span> REG_CLR_VAL<\/span>(reg,clrmask,pos) ((reg) &= ~((clrmask) << (pos)))\r\n#define<\/span> REG_SET_VAL<\/span>(reg,val,setmask,pos) do {\\\r\nREG_CLR_VAL<\/span>(reg,setmask,pos);\\\r\n((reg) |= ((val) << (pos))); \\\r\n}while(0)\r\n\r\n#define<\/span> REG_READ_VAL<\/span>(reg,rdmask,pos) ((REG_READ(reg) >> (pos)) & (rdmask))\r\n\r\n\r\n#endif<\/span> \/* REG_UTIL_H_ *\/<\/span><\/pre>\n
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On the other hand, <\/span>stm32f429xx.h<\/b> is the device header file. As shown in below code, this header file contains various peripheral register structures. For instance, the peripheral register structure explains various registers of the ADC peripheral. Understanding these structures is important to configure the microcontroller’s registers accurately and efficiently.<\/span><\/p>\n
#include <stdint.h>\r\n\r\n\/** @addtogroup Peripheral_registers_structures\r\n  * @{\r\n  *\/   \r\n\r\n\/** \r\n  * @brief Analog to Digital Converter  \r\n  *\/<\/span>\r\n\r\ntypedef struct<\/span>\r\n{\r\n  __IO uint32_t SR;     \/*!< ADC status register,                         Address offset: 0x00 *\/<\/span>\r\n  __IO uint32_t CR1;    \/*!< ADC control register 1,                      Address offset: 0x04 *\/<\/span>\r\n  __IO uint32_t CR2;    \/*!< ADC control register 2,                      Address offset: 0x08 *\/<\/span>\r\n  __IO uint32_t SMPR1;  \/*!< ADC sample time register 1,                  Address offset: 0x0C *\/<\/span>\r\n  __IO uint32_t SMPR2;  \/*!< ADC sample time register 2,                  Address offset: 0x10 *\/<\/span>\r\n  __IO uint32_t JOFR1;  \/*!< ADC injected channel data offset register 1, Address offset: 0x14 *\/<\/span>\r\n  __IO uint32_t JOFR2;  \/*!< ADC injected channel data offset register 2, Address offset: 0x18 *\/<\/span>\r\n  __IO uint32_t JOFR3;  \/*!< ADC injected channel data offset register 3, Address offset: 0x1C *\/<\/span>\r\n  __IO uint32_t JOFR4;  \/*!< ADC injected channel data offset register 4, Address offset: 0x20 *\/<\/span>\r\n  __IO uint32_t HTR;    \/*!< ADC watchdog higher threshold register,      Address offset: 0x24 *\/<\/span>\r\n  __IO uint32_t LTR;    \/*!< ADC watchdog lower threshold register,       Address offset: 0x28 *\/<\/span>\r\n  __IO uint32_t SQR1;   \/*!< ADC regular sequence register 1,             Address offset: 0x2C *\/<\/span>\r\n  __IO uint32_t SQR2;   \/*!< ADC regular sequence register 2,             Address offset: 0x30 *\/<\/span>\r\n  __IO uint32_t SQR3;   \/*!< ADC regular sequence register 3,             Address offset: 0x34 *\/<\/span>\r\n  __IO uint32_t JSQR;   \/*!< ADC injected sequence register,              Address offset: 0x38*\/<\/span>\r\n  __IO uint32_t JDR1;   \/*!< ADC injected data register 1,                Address offset: 0x3C *\/<\/span>\r\n  __IO uint32_t JDR2;   \/*!< ADC injected data register 2,                Address offset: 0x40 *\/<\/span>\r\n  __IO uint32_t JDR3;   \/*!< ADC injected data register 3,                Address offset: 0x44 *\/<\/span>\r\n  __IO uint32_t JDR4;   \/*!< ADC injected data register 4,                Address offset: 0x48 *\/<\/span>\r\n  __IO uint32_t DR;     \/*!< ADC regular data register,                   Address offset: 0x4C *\/<\/span>\r\n} ADC_TypeDef;\r\n\r\ntypedef struct<\/span>\r\n{\r\n  __IO uint32_t CSR;    \/*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 *\/<\/span>\r\n  __IO uint32_t CCR;    \/*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 *\/<\/span>\r\n  __IO uint32_t CDR;    \/*!< ADC common regular data register for dual\r\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 *\/<\/span>\r\n} ADC_Common_TypeDef;<\/pre>\n
 <\/p>\n
Moreover, <\/span>stm32f429xx.h<\/b> contains various base addresses of various blocks of the microcontroller. These addresses are crucial in configuring the microcontroller’s registers. Below code snippets show the base addresses for various blocks of the microcontroller.<\/span><\/p>\n
For instance, if we want to configure the Timer2 peripheral, its registers start from APB1PERIPH_BASE + 0x0000UL base. This is the base address of the registers of the Timer2 peripheral. Understanding these base addresses is essential in configuring the microcontroller’s registers accurately.<\/span><\/p>\n
\/** @addtogroup Peripheral_memory_map\r\n  * @{\r\n  *\/<\/span>\r\n#define<\/span> FLASH_BASE            0x08000000UL \/*!< FLASH(up to 2 MB) base address in the alias region<\/span>                         *\/<\/span>\r\n#define<\/span> CCMDATARAM_BASE       0x10000000UL \/*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  *\/<\/span>\r\n#define<\/span> SRAM1_BASE            0x20000000UL \/*!< SRAM1(112 KB) base address in the alias region                              *\/<\/span>\r\n#define<\/span> SRAM2_BASE            0x2001C000UL \/*!< SRAM2(16 KB) base address in the alias region                              *\/<\/span>\r\n#define<\/span> SRAM3_BASE            0x20020000UL \/*!< SRAM3(64 KB) base address in the alias region                              *\/<\/span>\r\n#define<\/span> PERIPH_BASE           0x40000000UL \/*!< Peripheral base address in the alias region                                *\/<\/span>\r\n#define<\/span> BKPSRAM_BASE          0x40024000UL \/*!< Backup SRAM(4 KB) base address in the alias region                         *\/<\/span>\r\n#define<\/span> FMC_R_BASE            0xA0000000UL \/*!< FMC registers base address                                                 *\/<\/span>\r\n#define<\/span> SRAM1_BB_BASE         0x22000000UL \/*!< SRAM1(112 KB) base address in the bit-band region                          *\/<\/span>\r\n#define<\/span> SRAM2_BB_BASE         0x22380000UL \/*!< SRAM2(16 KB) base address in the bit-band region                           *\/<\/span>\r\n#define<\/span> SRAM3_BB_BASE         0x22400000UL \/*!< SRAM3(64 KB) base address in the bit-band region                           *\/<\/span>\r\n#define<\/span> PERIPH_BB_BASE        0x42000000UL \/*!< Peripheral base address in the bit-band region                             *\/<\/span>\r\n#define<\/span> BKPSRAM_BB_BASE       0x42480000UL \/*!< Backup SRAM(4 KB) base address in the bit-band region            <\/span>          *\/<\/span>\r\n#define<\/span> FLASH_END             0x081FFFFFUL \/*!< FLASH end address                                               <\/span>           *\/<\/span>\r\n#define<\/span> FLASH_OTP_BASE        0x1FFF7800UL \/*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                *\/<\/span>\r\n#define<\/span> FLASH_OTP_END         0x1FFF7A0FUL \/*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 *\/<\/span>\r\n#define<\/span> CCMDATARAM_END        0x1000FFFFUL \/*!< CCM data RAM end address                                                   *\/<\/span>\r\n\r\n\/* Legacy defines *\/<\/span>\r\n#define<\/span> SRAM_BASE             SRAM1_BASE\r\n#define<\/span> SRAM_BB_BASE          SRAM1_BB_BASE\r\n\r\n\/*!< Peripheral memory map *\/\r\n<\/span>#define<\/span> APB1PERIPH_BASE       PERIPH_BASE\r\n#define<\/span> APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\r\n#define<\/span> AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\r\n#define<\/span> AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\r\n\r\n\/*!< APB1 peripherals *\/<\/span>\r\n#define<\/span> TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\r\n#define<\/span> TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\r\n#define<\/span> TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\r\n#define<\/span> TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\r\n#define<\/span> TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\r\n#define<\/span> TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\r\n#define<\/span> TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\r\n#define<\/span> TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\r\n#define<\/span> TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\r\n#define<\/span> RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\r\n#define<\/span> WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\r\n#define<\/span> IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\r\n#define<\/span> I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\r\n#define<\/span> SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\r\n#define<\/span> SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\r\n#define<\/span> I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\r\n#define<\/span> USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\r\n#define<\/span> USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\r\n#define<\/span> UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\r\n#define<\/span> UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\r\n#define<\/span> I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\r\n#define<\/span> I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\r\n#define<\/span> I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\r\n#define<\/span> CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\r\n#define<\/span> CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\r\n#define<\/span> PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\r\n#define<\/span> DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\r\n#define<\/span> UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)\r\n#define<\/span> UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)\r\n<\/pre>\n
 <\/p>\n
In the main program, we need to include these header files. We can use the following lines of code to include them:<\/span><\/p>\n
#include \u201cstm32f429xx.h\u201d<\/b><\/p>\n
#include \u201creg_util.h\u201d<\/b><\/p>\n
Then, we will write one function called <\/span>SystemClock_Setup()<\/b>. This function is responsible for setting up the main PLL.<\/span><\/p>\n
To do that, we need to access the RCC peripheral of the microcontroller. We can create a variable to access the RCC peripheral of the microcontroller. So, we need to access the registers of the RCC block. The base address of the RCC registers is available in the device header file. We can create a variable of the RCC structure <\/span>RCC_typedef<\/b>, which we will call <\/span>pRCC<\/b> and this is equal to the <\/span>RCC_BASE<\/b> address. We can define it like this:<\/span><\/p>\n
RCC_TypeDef  *pRCC = RCC;<\/b><\/p>\n
Once we have the <\/span>pRCC<\/b> pointer, we can set the value of PLLM. To do that, we have to access the <\/span>RCC_PLLCFGR<\/b> register, as shown in Figure 6. This is one of the registers of the RCC block. We have to configure the value of PLLM here by writing a new value to this register. Before doing that, we need to make sure that the PLLM bits are cleared first. This is important to avoid any unwanted values from previous configurations. To do that, we can use a macro called <\/span>REG_SET_VAL<\/b>, which takes the register value, a new value, a mask, and the position. The mask value is important as it helps clear the bits before setting a new value. The position value is the starting bit position of the value we want to set.<\/span><\/p>\n
We can use the following line of code to set the value of PLLM with a value of 8:<\/span><\/p>\n
REG_SET_VAL(pRCC->PLLCFGR, 0x8U, 0x3FU, 0U);<\/b><\/p>\n
\"Setting
Figure 1. main.c file<\/span><\/figcaption><\/figure>\n
 <\/p>\n
This line of code clears the register from the starting bit position using the mask value and sets the new value 0x8.<\/span><\/p>\n
\"Setting
Figure 2. RCC PLL configuration register<\/figcaption><\/figure>\n
Like that, we can write the rest of the code for PLL_N and PLL_P configuration. Configuring the PLL is essential in setting up the main clock, and it is just one part of a much more comprehensive process.<\/span><\/p>\n
 <\/p>\n
Reference manual<\/b><\/a><\/span><\/p>\n
Get the Full Course on STM32-LTDC, LCD-TFT, LVGL (MCU3)<\/b><\/span> Here.<\/b><\/a><\/span><\/p>\n
FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n
Click here: https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n
 <\/p>\n<\/div>\n
<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"
  Setting up main system clock code implementation part-1   In this article, we will begin creating the main clock code for our application. Having an accurate clock is essential for many applications and devices, and it’s no different in our case. The timekeeping module of our application is the backbone of the system, and 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part-1","ocean_post_subheading":"","ocean_post_title_style":"solid-color","ocean_post_title_background_color":"#0d64bc","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"off","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[],"class_list":["post-14428","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","entry","has-media"],"yoast_head":"\nSetting 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