{"id":14451,"date":"2023-04-21T09:40:34","date_gmt":"2023-04-21T04:10:34","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=14451"},"modified":"2023-09-07T12:46:58","modified_gmt":"2023-09-07T07:16:58","slug":"stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-18-setting-up-main-system-clock-code-implementation-part-2","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-18-setting-up-main-system-clock-code-implementation-part-2\/","title":{"rendered":"STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 18| Setting up main system clock code implementation part-2"},"content":{"rendered":"<div class=\"boldgrid-section color4-background-color color-4-text-contrast bg-background-color\">\n<div class=\"container\">\n<div class=\"row\">\n<div class=\"col-lg-1 col-md-12 col-sm-12 col-xs-12\"><\/div>\n<div class=\"col-lg-10 col-md-12 col-xs-12 col-sm-12\">\n<p class=\"\">&nbsp;<\/p>\n<h1 class=\"\" style=\"text-align: center; font-size: 38px;\"><span style=\"color: #000080;\"><b>Setting up main system clock code implementation part-2<\/b><\/span><\/h1>\n<div class=\"row bg-editor-hr-wrap\">\n<div class=\"col-lg-12 col-md-12 col-xs-12 col-sm-12\">\n<div>\n<div class=\"bg-hr bg-hr-16 color2-color\" style=\"border-style: solid; border-width: 0px 0px 2px;\"><\/div>\n<p>&nbsp;<\/p>\n<\/div>\n<\/div>\n<\/div>\n<p class=\"\" style=\"font-size: 17px; line-height: 30px; font-family: 'Roboto Slab'; font-weight: 400;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">The process of setting up the PLL_M, PLL_N, and PLL_P codes is depicted below.<\/span><\/p>\n<pre class=\"color-5-text-contrast color5-background-color\" style=\"box-shadow: #cecece 0px 0px 0px 0px inset;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\"><span style=\"color: #993366;\">void<\/span> SystemClock_Setup(<span style=\"color: #993366;\">void<\/span>)\r\n\r\n{\r\n\r\n<span style=\"color: #339966;\">RCC_TypeDef<\/span> *pRCC = RCC;\r\n\r\n<span style=\"color: #339966;\">\/\/ Setting up main PLL<\/span>\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,0x8U,0x3FU,0U); <span style=\"color: #339966;\">\/*PLL_M*\/<\/span>\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,180U,0x1FFU,6U); <span style=\"color: #339966;\">\/*PLL_N*\/<\/span>\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,0x00U,0x3U,16U); <span style=\"color: #339966;\">\/*PLL_P*\/<\/span><\/pre>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">To elaborate on this process, line 45 utilizes the value of 180 for PLL_N and a mask value of 1FF. It is important to note that the position for PLL_N begins at 6. For PLL_P, the value is set to 0, as opposed to 2.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">According to the <\/span><span style=\"color: #000080;\"><a style=\"color: #000080;\" href=\"https:\/\/www.st.com\/resource\/en\/reference_manual\/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf\"><span style=\"font-weight: 400;\">reference manual<\/span><\/a><\/span><span style=\"font-weight: 400;\">, if PLLP is 0 and the bit positions are also 0, then it&#8217;s equal to 2.<\/span><\/span><\/p>\n<figure id=\"attachment_14455\" aria-describedby=\"caption-attachment-14455\" style=\"width: 729px\" class=\"wp-caption aligncenter\"><img fetchpriority=\"high\" decoding=\"async\" class=\"wp-image-14455 \" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-2-9.png\" alt=\"Figure 2. PLLP reference manual\" width=\"729\" height=\"359\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9.png 1841w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9-300x148.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9-1024x504.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9-768x378.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9-600x296.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-9-1536x757.png 1536w\" sizes=\"(max-width: 729px) 100vw, 729px\" \/><figcaption id=\"caption-attachment-14455\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 2. PLLP reference manual<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Using RCC block, you can utilize the macros given by the device header file, as shown in below(<span style=\"color: #000000;\">Instead of bit positions use macros)<\/span>. This includes the use of RCC_PLLCFGR_PLLM_Pos for M, RCC_PLLCFGR_PLLN_pos for N, and RCC_PLLCFGR_PLLP_Pos for P.<\/span><\/p>\n<pre class=\"color-5-text-contrast color5-background-color\" style=\"box-shadow: #cecece 0px 0px 0px 0px;\"><span style=\"color: #993366;\">void<\/span> SystemClock_Setup(<span style=\"color: #993366;\">void<\/span>)\r\n\r\n{\r\n\r\n<span style=\"color: #339966;\">RCC_TypeDef<\/span> *pRCC = RCC;\r\n\r\n<span style=\"color: #339966;\">\/\/ Setting up main PLL<\/span>\r\n\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,0x8U,0x3FU,RCC_PLLCFGR_PLLM_Pos); <span style=\"color: #339966;\">\/*PLL_M*\/<\/span>\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,180U,0x1FFU,RCC_PLLCFGR_PLLN_Pos); <span style=\"color: #339966;\">\/*PLL_N*\/<\/span>\r\nREG_SET_VAL(pRCC-&gt;PLLCFGR,0x00U,0x3U,RCC_PLLCFGR_PLLP_Pos); <span style=\"color: #339966;\">\/*PLL_P*\/<\/span><\/pre>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Our next task is to focus on the clock tree. While we have configured the values for M, P, and N, it is important to note that our system clock is not necessarily set to 180 megahertz. To turn on this PLL, we will need to perform this step later.<\/span><\/p>\n<figure id=\"attachment_14457\" aria-describedby=\"caption-attachment-14457\" style=\"width: 772px\" class=\"wp-caption aligncenter\"><img decoding=\"async\" class=\"wp-image-14457 \" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-4-7.png\" alt=\"Figure 4. Clock tree\" width=\"772\" height=\"469\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-7.png 1377w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-7-300x182.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-7-1024x622.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-7-768x467.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-7-600x365.png 600w\" sizes=\"(max-width: 772px) 100vw, 772px\" \/><figcaption id=\"caption-attachment-14457\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 4. Clock tree<\/span><\/figcaption><\/figure>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">It is important to note that the PLL engine creates our DOTCLK at a frequency of 6MHz for this task.&nbsp;<\/span><\/p>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">We must determine the necessary DOTCLK frequency that the display module requires; this is dependent on the display module&#8217;s capability. A high-speed DOTCLK may cause the display module to fail to interpret such a high-frequency clock.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">To determine the necessary DOTCLK frequency, we can consult the datasheet of the ILI9341, which provides information on clock frequencies on page 46, assuming a clock frequency of 6.35MHz (as shown in Figure 5).<\/span><\/p>\n<figure id=\"attachment_14458\" aria-describedby=\"caption-attachment-14458\" style=\"width: 704px\" class=\"wp-caption aligncenter\"><img decoding=\"async\" class=\"wp-image-14458 \" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-5-4.png\" alt=\"Figure 5. Table\" width=\"704\" height=\"217\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-4.png 869w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-4-300x93.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-4-768x237.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-4-600x185.png 600w\" sizes=\"(max-width: 704px) 100vw, 704px\" \/><figcaption id=\"caption-attachment-14458\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 5. Table<\/span><\/figcaption><\/figure>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">We should use the pixel clock of 6 to 7MHz for this controller.<\/span><\/p>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Additionally, if we are using this driver chip, OTA5180A, which is being used in STM32F7 Discovery Board.&nbsp;<\/span><\/p>\n<figure id=\"attachment_14459\" aria-describedby=\"caption-attachment-14459\" style=\"width: 726px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14459\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-6-5.png\" alt=\"Setting up main system clock code implementation part-2\" width=\"726\" height=\"684\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-6-5.png 1073w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-6-5-300x283.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-6-5-1024x965.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-6-5-768x724.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-6-5-600x565.png 600w\" sizes=\"(max-width: 726px) 100vw, 726px\" \/><figcaption id=\"caption-attachment-14459\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 6. Clock and data input timing diagram<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Here, in this table(Figure 7), you can see that the maximum value for DCLK frequency is 12MHz.&nbsp;<\/span><\/p>\n<figure id=\"attachment_14460\" aria-describedby=\"caption-attachment-14460\" style=\"width: 755px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14460\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-7-3.png\" alt=\"Setting up main system clock code implementation part-2\" width=\"755\" height=\"498\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-7-3.png 917w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-7-3-300x198.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-7-3-768x507.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-7-3-600x396.png 600w\" sizes=\"(max-width: 755px) 100vw, 755px\" \/><figcaption id=\"caption-attachment-14460\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 7.Parallel RGB Input Timing Table<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400;\"><span style=\"color: #000000;\">When it comes to PLLSAI, we must refer to the RCC PLL configuration register, as shown in Figure 8, to configure R and N.<\/span>&nbsp;<\/span><\/p>\n<figure id=\"attachment_14461\" aria-describedby=\"caption-attachment-14461\" style=\"width: 736px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14461\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-8-2.png\" alt=\"Setting up main system clock code implementation part-2\" width=\"736\" height=\"371\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2.png 1737w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2-300x151.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2-1024x516.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2-768x387.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2-600x302.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-8-2-1536x774.png 1536w\" sizes=\"(max-width: 736px) 100vw, 736px\" \/><figcaption id=\"caption-attachment-14461\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 8. RCC PLL configuration register(RCC_PLLSAICFGR)<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400;\">Furthermore, we can use RCC Dedicated Clock Configuration Register (Figure 9) for the divider, with its value must be between 2 to 16 to control the frequency of LCD_CLK.<\/span><\/p>\n<figure id=\"attachment_14462\" aria-describedby=\"caption-attachment-14462\" style=\"width: 690px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14462\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-9-2.png\" alt=\"Setting up main system clock code implementation part-2\" width=\"690\" height=\"304\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2.png 1714w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2-300x132.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2-1024x450.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2-768x338.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2-600x264.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-9-2-1536x676.png 1536w\" sizes=\"(max-width: 690px) 100vw, 690px\" \/><figcaption id=\"caption-attachment-14462\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 9. RCC dedicated clock configuration register(RCC_DCKCFGR)<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-size: 18px; line-height: 30px; font-family: 'Roboto Slab'; font-weight: 400;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #800080;\"><b>Get the Full Course on STM32-LTDC, LCD-TFT, LVGL (MCU3)<\/b><span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https:\/\/www.udemy.com\/course\/mastering-microcontroller-stm32-ltdc-lcd-tft-lvgl\/\"> <b>Here.<\/b><\/a><\/span><\/span><\/p>\n<p class=\"\" style=\"font-size: 25px; font-family: 'Roboto Slab'; font-weight: 400; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000080;\"><b>FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n<p class=\"\" style=\"font-size: 17px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000000;\">Click here:<\/span>&nbsp;<span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https:\/\/fastbitlab.com\/course1\" target=\"_blank\" rel=\"noopener\">https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n<p class=\"\">&nbsp;<\/p>\n<\/div>\n<div class=\"col-lg-1 col-md-12 col-sm-12 col-xs-12\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; Setting up main system clock code implementation part-2 &nbsp; The process of setting up the PLL_M, PLL_N, and PLL_P codes is depicted below. void SystemClock_Setup(void) { RCC_TypeDef *pRCC = RCC; \/\/ Setting up main PLL REG_SET_VAL(pRCC-&gt;PLLCFGR,0x8U,0x3FU,0U); \/*PLL_M*\/ REG_SET_VAL(pRCC-&gt;PLLCFGR,180U,0x1FFU,6U); \/*PLL_N*\/ REG_SET_VAL(pRCC-&gt;PLLCFGR,0x00U,0x3U,16U); \/*PLL_P*\/ &nbsp; To elaborate on this process, line 45 utilizes the value of 180 [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":14458,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"enable","ocean_disable_heading":"default","ocean_post_title":"Setting up main system clock code implementation part-2","ocean_post_subheading":"","ocean_post_title_style":"solid-color","ocean_post_title_background_color":"#0066a5","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"off","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[],"class_list":["post-14451","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","entry","has-media"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Main System Clock Setup and PLL Parameters for MCU<\/title>\n<meta name=\"description\" content=\"Main system clock setup using PLL_M, PLL_N, and PLL_P codes for optimal MCU performance. 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