{"id":14507,"date":"2023-04-24T11:28:46","date_gmt":"2023-04-24T05:58:46","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=14507"},"modified":"2023-09-07T12:51:44","modified_gmt":"2023-09-07T07:21:44","slug":"stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-20-setting-up-main-system-clock-code-implementation-part-4","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-20-setting-up-main-system-clock-code-implementation-part-4\/","title":{"rendered":"STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 20| Setting up main system clock code implementation part-4"},"content":{"rendered":"<div class=\"boldgrid-section color4-background-color color-4-text-contrast bg-background-color\">\n<div class=\"container\">\n<div class=\"row\">\n<div class=\"col-lg-1 col-md-12 col-sm-12 col-xs-12\"><\/div>\n<div class=\"col-lg-10 col-md-12 col-xs-12 col-sm-12\">\n<p class=\"\">&nbsp;<\/p>\n<h1 class=\"\" style=\"text-align: center; font-size: 38px; font-family: 'Roboto Slab'; font-weight: 400; line-height: 50px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000080;\"><b>Setting up main system clock code implementation part-4<\/b><\/span><\/h1>\n<div class=\"row bg-editor-hr-wrap\">\n<div class=\"col-lg-12 col-md-12 col-xs-12 col-sm-12\">\n<div>\n<div class=\"bg-hr bg-hr-16 color2-color\" style=\"border-style: solid; border-width: 0px 0px 2px;\"><\/div>\n<p>&nbsp;<\/p>\n<\/div>\n<\/div>\n<\/div>\n<p class=\"\" style=\"font-size: 20px; font-family: 'Roboto Slab'; font-weight: 400;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"text-decoration: underline; color: #000080;\"><b>Setup main system clock(SYSCLK)<\/b><\/span><\/p>\n<ul class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\">\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Configure main PLL parameters<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Configure PLLSAI parameters<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Configure AHB, APBx prescalers<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Turn on the main PLL<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Wait until PLLCLK ready bit is set<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Switch PLLCLK as SYSCLK<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Wait for switch status<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Configure FLASH wait states:<\/span>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"2\"><span style=\"font-weight: 400; color: #000000;\">To correctly read data from Flash memory, the number of wait states(LATENCY) must be correctly programmed in the Flash access control register(FLASH_ACR) according to the frequency of the CPU clock(HCLK) and the supply voltage of the device.<\/span><\/li>\n<\/ul>\n<\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Turn on PLLSAI<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400; color: #000000;\">Wait until PLLSAICLK ready bit is set<\/span><\/li>\n<\/ul>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">We completed the above three steps in the previous article. The next step is to Turn on the main PLL<\/span><span style=\"font-weight: 400;\">. Once you have turned on the PLL, you need to wait until the PLL clock is generated, which can take some time. You should wait until the PLLCLK ready bit is set, indicating that the PLLCLK is ready.&nbsp;<\/span><\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Once the PLLCLK bit is set, that means the PLL clock is ready and you have to switch PLLCLK as SYSCLK, that is the main system clock.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Next, you should wait for the switch status. It may take some time for the microcontroller to make the switch. After that, you need to perform one more important step here.<\/span><\/p>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Since you have increased the HCLK, the Flash memory may not respond to such a high frequency. The Flash read may fail or the bus may return an error or something like that.&nbsp;<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">That&#8217;s why, what this reference manual says is, to correctly read data from Flash memory, the number of wait states(LATENCY) must be correctly programmed in the Flash access control register(FLASH_ACR) according to the frequency of the CPU clock(HCLK) and the supply voltage of the device.<\/span><\/p>\n<figure id=\"attachment_14510\" aria-describedby=\"caption-attachment-14510\" style=\"width: 669px\" class=\"wp-caption aligncenter\"><img fetchpriority=\"high\" decoding=\"async\" class=\"wp-image-14510 \" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-1-9.png\" alt=\"Figure 1. Configure FLASH read latency\" width=\"669\" height=\"392\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9.png 1598w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9-300x176.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9-1024x600.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9-768x450.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9-600x351.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-1-9-1536x900.png 1536w\" sizes=\"(max-width: 669px) 100vw, 669px\" \/><figcaption id=\"caption-attachment-14510\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 1. Configure FLASH read latency<\/span><\/figcaption><\/figure>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">You can find this table in the<\/span><span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https:\/\/www.st.com\/resource\/en\/reference_manual\/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf\"><span style=\"font-weight: 400;\"> reference manual<\/span><\/a><\/span><span style=\"font-weight: 400;\"> under the section &#8220;Embedded Flash Memory&#8221;. From this table, you can see that our voltage range falls between 2.7V &#8211; 3.6V and our HCLK falls between 150&lt;HCLK\u2264180. Therefore, you need to program 6 CPU cycles of latency into the flash control register. This means you have to program the value 5 into the FLASH_ACR register.<\/span><\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">After that, you may turn on the PLLSAI because we need the LCD_CLK to be active. Wait until the PLLSAICLK is ready.&nbsp;<\/span><\/p>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Let me now show you the place where you can carry out these steps.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">RCC clock control register, as shown in Figure 2.<\/span><\/p>\n<figure id=\"attachment_14511\" aria-describedby=\"caption-attachment-14511\" style=\"width: 631px\" class=\"wp-caption aligncenter\"><img decoding=\"async\" class=\"wp-image-14511 \" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-2-11.png\" alt=\"Figure 2. RCC clock control register(RCC_CR)\" width=\"631\" height=\"302\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11.png 1789w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11-300x144.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11-1024x491.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11-768x368.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11-600x287.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-2-11-1536x736.png 1536w\" sizes=\"(max-width: 631px) 100vw, 631px\" \/><figcaption id=\"caption-attachment-14511\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 2. RCC clock control register(RCC_CR)<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Here, you will find the PLLON bit that you can toggle to turn on the PLL. Additionally, you will find the PLLRDY bit that you should wait for to be set before proceeding. Similarly, to turn on the PLLSAI block, use the PLLSAI ON bit, and wait for the PLLSAI RDY bit to be set. This will indicate that the clock is ready.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Once the PLLRDY bit is set, you need to switch to another bit. Where can you find the switch bit? Let&#8217;s navigate to the RCC clock configuration register. You can find the switch (SW) there.<\/span><\/p>\n<figure id=\"attachment_14512\" aria-describedby=\"caption-attachment-14512\" style=\"width: 712px\" class=\"wp-caption aligncenter\"><img decoding=\"async\" class=\"wp-image-14512\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-3-9.png\" alt=\"Setup main system clock(SYSCLK)\" width=\"712\" height=\"344\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9.png 1723w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9-300x145.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9-1024x495.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9-768x371.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9-600x290.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-3-9-1536x743.png 1536w\" sizes=\"(max-width: 712px) 100vw, 712px\" \/><figcaption id=\"caption-attachment-14512\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 3. RCC clock configuration register(RCC_CFGR)<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">You have to use two-bit fields, namely SW and SWS.&nbsp;<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">Therefore, you have to set SW switch to 10(one zero). That means, PLL selected as system clock. Once you do that, you have to wait until the System clock switch status is updated by the microcontroller.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">You can see that, it is set and cleared by the hardware. So, the software cannot modify these bits. It is read-only. Hardware updates these fields.<\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">So, if this bit field gives you the value 2, that is one zero(10), which means, PLL used as the system clock.&nbsp;<\/span><\/p>\n<figure id=\"attachment_14513\" aria-describedby=\"caption-attachment-14513\" style=\"width: 728px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14513\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-4-9.png\" alt=\"Setup main system clock(SYSCLK)\" width=\"728\" height=\"364\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9.png 1715w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9-300x150.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9-1024x512.png 1024w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9-768x384.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9-600x300.png 600w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-4-9-1536x768.png 1536w\" sizes=\"(max-width: 728px) 100vw, 728px\" \/><figcaption id=\"caption-attachment-14513\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 4. SWS and SW switch<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 20px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #ff0000;\"><strong>How do you access the flash registers?<\/strong><\/span><\/p>\n<p class=\"\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"font-weight: 400; color: #000000;\">For that, you have to get the base address from where the registers of the Flash start in the memory map of the microcontroller. For that, you have to use the flash register definition structure.&nbsp;<\/span><\/p>\n<pre class=\"color-5-text-contrast color5-background-color\" style=\"font-family: 'Roboto Slab'; font-weight: 400; font-size: 17px; line-height: 30px; box-shadow: #cecece 0px 0px 0px 0px inset;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\"><span style=\"color: #000000;\"><span style=\"color: #339966;\">FLASH_TypeDef<\/span> <\/span>*pFlash = FLASH;<\/pre>\n<figure id=\"attachment_14514\" aria-describedby=\"caption-attachment-14514\" style=\"width: 720px\" class=\"wp-caption aligncenter\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-14514\" src=\"https:\/\/fastbitlab.com\/wp-content\/uploads\/2023\/04\/Figure-5-6.png\" alt=\" Setup main system clock(SYSCLK)\" width=\"720\" height=\"395\" srcset=\"https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-6.png 1018w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-6-300x165.png 300w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-6-768x422.png 768w, https:\/\/fastbitlab.com\/blog\/wp-content\/uploads\/2023\/04\/Figure-5-6-600x329.png 600w\" sizes=\"(max-width: 720px) 100vw, 720px\" \/><figcaption id=\"caption-attachment-14514\" class=\"wp-caption-text\"><span style=\"color: #000000;\">Figure 5. Flash register<\/span><\/figcaption><\/figure>\n<p class=\"\">&nbsp;<\/p>\n<p class=\"\" style=\"font-size: 18px; line-height: 30px; font-family: 'Roboto Slab'; font-weight: 400;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #800080;\"><b>Get the Full Course on STM32-LTDC, LCD-TFT, LVGL (MCU3)<\/b><\/span><span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https:\/\/www.udemy.com\/course\/mastering-microcontroller-stm32-ltdc-lcd-tft-lvgl\/\"> <b>Here.<\/b><\/a><\/span><\/p>\n<p class=\"\" style=\"font-size: 20px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000080;\"><b>FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n<p class=\"\" style=\"font-size: 17px; line-height: 30px;\" data-font-family=\"Roboto Slab\" data-font-weight=\"400\" data-font-style=\"\"><span style=\"color: #000000;\">Click here:<\/span>&nbsp;<span style=\"color: #0000ff;\"><a style=\"color: #0000ff;\" href=\"https:\/\/fastbitlab.com\/course1\" target=\"_blank\" rel=\"noopener\">https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n<p>&nbsp;<\/p>\n<\/div>\n<div class=\"col-lg-1 col-md-12 col-sm-12 col-xs-12\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; Setting up main system clock code implementation part-4 &nbsp; Setup main system clock(SYSCLK) Configure main PLL parameters Configure PLLSAI parameters Configure AHB, APBx prescalers Turn on the main PLL Wait until PLLCLK ready bit is set Switch PLLCLK as SYSCLK Wait for switch status Configure FLASH wait states: To correctly read data from Flash [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":14510,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"Setting up main system clock code implementation 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This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Setup main system clock(SYSCLK) |STM32-LTDC, LCD-TFT, LVGL<\/title>\n<meta name=\"description\" content=\"Learn how to set up the main system clock (SYSCLK) using PLL, configure Flash latency, and access Flash memory registers on STM32\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-20-setting-up-main-system-clock-code-implementation-part-4\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Setup main system clock(SYSCLK) |STM32-LTDC, LCD-TFT, LVGL\" \/>\n<meta property=\"og:description\" content=\"Learn how to set up the main system clock (SYSCLK) using PLL, configure Flash latency, and access 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