{"id":14547,"date":"2023-04-28T10:17:41","date_gmt":"2023-04-28T04:47:41","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=14547"},"modified":"2023-08-17T09:55:01","modified_gmt":"2023-08-17T04:25:01","slug":"stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-22-setting-up-main-system-clock-code-implementation-part-6","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-22-setting-up-main-system-clock-code-implementation-part-6\/","title":{"rendered":"STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 22| Setting up main system clock code implementation part-6"},"content":{"rendered":"
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Setting up main system clock code implementation part-6<\/b><\/span><\/h1>\n
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SystemClock_Setup code for STM32F407 Discovery Board <\/span><\/strong><\/span><\/p>\n

void<\/span> SystemClock_Setup(void)\r\n\r\n{\r\n\r\nRCC_TypeDef<\/span> *pRCC = RCC;\r\nFLASH_TypeDef<\/span> *pFlash = FLASH;\r\nPWR_TypeDef<\/span> *pPWR = PWR;\r\n\r\n\/\/1. Program flash wait states<\/span>\r\nREG_SET_VAL(pFlash->ACR<\/span>,0x5U,0xFU,FLASH_ACR_LATENCY_Pos);\r\n\r\n\/\/2. Over drive settings<\/span>\r\nREG_SET_BIT(pRCC->APB1ENR<\/span>,RCC_APB1ENR_PWREN_Pos); \/*Enable clock for PWR register access*\/<\/span>\r\nREG_SET_BIT(pPWR->CR<\/span>,PWR_CR_VOS_Pos); \/*VOS = 1*\/<\/span>\r\n\r\n\/\/3. Setting up main PLL<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,0x8U,0x3FU,RCC_PLLCFGR_PLLM_Pos); \/*PLL_M*\/<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,168U,0x1FFU,RCC_PLLCFGR_PLLN_Pos); \/*PLL_N*\/<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,0x00U,0x3U,RCC_PLLCFGR_PLLP_Pos); \/*PLL_P*\/<\/span>\r\n\r\n\/\/5. Setting up AHB and APBx clocks<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0U,0xFU,RCC_CFGR_HPRE_Pos); \/*AHB prescaler*\/<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x5U,0x7U,RCC_CFGR_PPRE1_Pos); \/*APB1 prescaler*\/<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x4U,0x7U,RCC_CFGR_PPRE2_Pos); \/*APB2 prescaler*\/<\/span>\r\n\r\n\/\/6. Turn on PLL and wait for PLLCLK ready<\/span>\r\nREG_SET_BIT(pRCC->CR<\/span>,RCC_CR_PLLON_Pos);\r\nwhile<\/span>(!REG_READ_BIT(pRCC->CR<\/span>,RCC_CR_PLLRDY_Pos));\r\n\r\n\/\/7. Switch PLLCLK as SYSCLK<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x2U,0x3U,RCC_CFGR_SW_Pos);\r\nwhile<\/span>(!(REG_READ_VAL(pRCC->CFGR<\/span>,0x3U,RCC_CFGR_SWS_Pos) == 0x2U));\r\n\r\n}<\/pre>\n
The code is pretty much the same compared to the previous one(SystemClock_Setup code for stm32f429 discovery). In the Overdrive settings, we modified some code. <\/span><\/p>\n
In this microcontroller, the maximum speed you can achieve is 168MHz. That’s why, I have modified this line here for the PLL_N entry. <\/span><\/p>\n
And apart from that, all these codes remain the same.<\/span><\/p>\n
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SystemClock_Setup code for STM32F746 Discovery Board<\/span><\/strong><\/span><\/p>\n
Below code snippet shows how the system clock setup code looks in the STM32F746 Discovery board. <\/span><\/p>\n
void<\/span> SystemClock_Setup(void<\/span>)\r\n{\r\nRCC_TypeDef<\/span> *pRCC = RCC;\r\nFLASH_TypeDef<\/span> *pFlash = FLASH;\r\nPWR_TypeDef<\/span> *pPWR = PWR;\r\n\r\n\/\/1. Program flash wait states<\/span>\r\nREG_SET_VAL(pFlash->ACR<\/span>,0x7U,0xFU,FLASH_ACR_LATENCY_Pos);\r\n\r\n\/\/2. Over drive settings<\/span>\r\nREG_SET_BIT(pRCC->APB1ENR<\/span>,RCC_APB1ENR_PWREN_Pos); \/*Enable clock for PWR register access*\/<\/span>\r\nREG_SET_VAL(pPWR->CR1<\/span>,0x3,0x3,PWR_CR1_VOS_Pos); \/*VOS = 0b11*\/<\/span>\r\nREG_SET_BIT(pPWR->CR1<\/span>,PWR_CR1_ODEN_Pos); \/* Activate over drive mode *\/<\/span>\r\nwhile<\/span>(! REG_READ_BIT(pPWR->CSR<\/span>1,PWR_CSR1_ODRDY_Pos)); \/* wait for overdrive ready*\/<\/span>\r\nREG_SET_BIT(pPWR->CR1<\/span>,PWR_CR1_ODSWEN_Pos); \/* Over drive switch enable*\/<\/span>\r\n\r\n\/\/3. Setting up main PLL<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,0x8U,0x3FU,RCC_PLLCFGR_PLLM_Pos); \/*PLL_M*\/<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,216U,0x1FFU,RCC_PLLCFGR_PLLN_Pos); \/*PLL_N*\/<\/span>\r\nREG_SET_VAL(pRCC->PLLCFGR<\/span>,0x00U,0x3U,RCC_PLLCFGR_PLLP_Pos); \/*PLL_P*\/<\/span>\r\n\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/This step is only required if you are using RGB interface \/\/\/\/\/\/\/\/\/\/\/\/<\/span>\r\n\/\/4. Setting up LCD_CLK using PLLSAI block<\/span>\r\nREG_SET_VAL(pRCC->PLLSAICFGR<\/span>,50U,0x1FFU,RCC_PLLSAICFGR_PLLSAIN_Pos); \/*PLLSAI_N*\/<\/span>\r\nREG_SET_VAL(pRCC->PLLSAICFGR<\/span>,0x02U,0x7U,RCC_PLLSAICFGR_PLLSAIR_Pos); \/*PLLSAI_R*\/<\/span>\r\nREG_SET_VAL(pRCC->DCKCFGR1<\/span>,0x00u,0x3U,RCC_DCKCFGR1_PLLSAIDIVR_Pos); \/*DIV*\/<\/span>\r\nREG_SET_BIT(pRCC->CR<\/span>,RCC_CR_PLLSAION_Pos);\r\nwhile(!REG_READ_BIT(pRCC->CR<\/span>,RCC_CR_PLLSAIRDY_Pos));\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/<\/span>\r\n\r\n\/\/5. Setting up AHB and APBx clocks<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0U,0xFU,RCC_CFGR_HPRE_Pos); \/*AHB prescaler*\/<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x5U,0x7U,RCC_CFGR_PPRE1_Pos); \/*APB1 prescaler*\/<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x4U,0x7U,RCC_CFGR_PPRE2_Pos); \/*APB2 prescaler*\/<\/span>\r\n\r\n\/\/6. Turn on PLL and wait for PLLCLK ready<\/span>\r\nREG_SET_BIT(pRCC->CR<\/span>,RCC_CR_PLLON_Pos);\r\nwhile<\/span>(!REG_READ_BIT(pRCC->CR<\/span>,RCC_CR_PLLRDY_Pos));\r\n\r\n\/\/7. Switch PLLCLK as SYSCLK<\/span>\r\nREG_SET_VAL(pRCC->CFGR<\/span>,0x2U,0x3U,RCC_CFGR_SW_Pos);\r\nwhile<\/span>(!(REG_READ_VAL(pRCC->CFGR<\/span>,0x3U,RCC_CFGR_SWS_Pos) == 0x2U));\r\n\r\n}<\/pre>\n
In this microcontroller, the maximum speed that you can achieve is, 216 MHz(line 217).<\/span><\/p>\n
And also, we have to produce the LCD_CLK by using the PLLSAI block of the RCC. <\/span><\/p>\n
So, please compare your code with this code. And you can also verify the clock by using an oscilloscope. For that, you have to route this clock via some microcontroller pin. So, that feature is available in the microcontroller. And if you just explore the RCC section of the reference manual<\/a><\/span>, they have mentioned how to route the clock via the microcontroller pins for measurement purposes.<\/span><\/p>\n
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FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n
Click here: <\/span>https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n
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  Setting up main system clock code implementation part-6   SystemClock_Setup code for STM32F407 Discovery Board  void SystemClock_Setup(void) { RCC_TypeDef *pRCC = RCC; FLASH_TypeDef *pFlash = FLASH; PWR_TypeDef *pPWR = PWR; \/\/1. Program flash wait states REG_SET_VAL(pFlash->ACR,0x5U,0xFU,FLASH_ACR_LATENCY_Pos); \/\/2. Over drive settings REG_SET_BIT(pRCC->APB1ENR,RCC_APB1ENR_PWREN_Pos); \/*Enable clock for PWR register access*\/ REG_SET_BIT(pPWR->CR,PWR_CR_VOS_Pos); \/*VOS = 1*\/ \/\/3. Setting up […]<\/p>\n","protected":false},"author":1,"featured_media":14551,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"enable","ocean_disable_heading":"default","ocean_post_title":"Setting up main system clock code implementation part-6","ocean_post_subheading":"","ocean_post_title_style":"solid-color","ocean_post_title_background_color":"#004093","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"off","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[],"class_list":["post-14547","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","entry","has-media"],"yoast_head":"\nSystem Clock Setup code for STM32F407 Discovery Board\u00a0<\/title>\n<meta name=\"description\" content=\"Learn how to efficiently configure the system clock on the STM32F407 Discovery board using code implementation. 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