{"id":14685,"date":"2023-05-15T11:55:23","date_gmt":"2023-05-15T06:25:23","guid":{"rendered":"https:\/\/fastbitlab.com\/?p=14685"},"modified":"2023-08-17T10:55:28","modified_gmt":"2023-08-17T05:25:28","slug":"stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-28-spi-peripheral-configuration-coding","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/stm32-ltdc-lcd-tft-lvgl-mcu3-lecture-28-spi-peripheral-configuration-coding\/","title":{"rendered":"STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 28| SPI peripheral configuration coding"},"content":{"rendered":"
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SPI peripheral configuration coding<\/b><\/span><\/h1>\n
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 <\/p>\n<\/div>\n<\/div>\n<\/div>\n

In this article, let’s do the SPI_Init function.<\/span><\/p>\n

Here we do a microcontroller SPI configuration for controller mode.<\/span><\/p>\n

\"Figure
Figure 1. SPI peripheral configuration code<\/span><\/figcaption><\/figure>\n

The code provided shows the initialization and configuration of the SPI (Serial Peripheral Interface) peripheral on a microcontroller, as shown in Figure 1.<\/span><\/p>\n

 <\/p>\n

To begin, we need to activate the peripheral clock for the SPI. The first step is to call the function LCD_SPI_Enable(), which sets the SPE (SPI Enable) bit in the CR1 (Control Register 1) of the SPI peripheral. This function doesn’t require any arguments, but it uses a pointer to the SPI peripheral, which we declare as pSPI. Here’s how the function looks:<\/span><\/p>\n

void LCD_SPI_Enable(void) <\/b>{ <\/b><\/span><\/p>\n

SPI_TypeDef *pSPI = SPI; <\/b><\/span><\/p>\n

REG_SET_BIT(pSPI->CR1, SPI_CR1_SPE_Pos);<\/b><\/span><\/p>\n

}<\/b><\/span><\/p>\n

This function is called to enable the SPI peripheral for communication with an LCD controller.<\/span><\/p>\n

 <\/p>\n

The second function, <\/span>LCD_SPI_Init()<\/span>, initializes and configures the SPI peripheral. <\/span><\/span><\/p>\n

SPI_TypeDef *pSPI = SPI; <\/b><\/span><\/p>\n

RCC_TypeDef *pRCC = RCC;<\/b><\/span><\/p>\n

These two lines define pointers to the SPI and RCC (Reset and Clock Control) peripheral registers.<\/span><\/p>\n

 <\/p>\n

The following code lines configure the SPI peripheral. Firstly, the SPI clock is enabled by setting the SPI5EN bit in the AHB2ENR (Advanced High-Performance Bus 2 Enable Register) of the RCC (Reset and Clock Control) peripheral. To do this, it is necessary to locate the SPI5 peripheral on the memory map and determine which bus domain it belongs to. To find this information, refer to the reference manual and navigate to the memory map. It can be observed that in our microcontroller, the SPI5 peripheral is part of the APB2 bus domain.<\/span><\/p>\n

\"Figure
Figure 2. Memory map<\/span><\/figcaption><\/figure>\n

REG_SET_BIT(pRCC-> AHB2ENR, RCC_APB2ENR_SPI5EN_Pos);<\/b><\/span><\/p>\n

This line sets a bit in the AHB2ENR register of the RCC peripheral to enable the clock for the SPI5 peripheral (this register is used to enable the clock to different peripherals).<\/span><\/p>\n

 <\/p>\n

Let’s check the SPI registers in the reference manual.<\/span><\/p>\n

\"Figure
Figure 3. SPI register<\/span><\/figcaption><\/figure>\n

Let’s start with the first register, which is the control register(CR1). Control registers are used to control the peripheral. So, it has various bits here. So, let’s go as per our discussion.<\/span><\/p>\n

 <\/p>\n

First, set the SPI mode to half-duplex controller mode. Remember, the \u2018controller\u2019 is the new word used for \u2018master\u2019.<\/span> <\/span><\/p>\n

 <\/p>\n

Master selection or controller selection(MSTR):<\/b><\/span><\/p>\n

You have to set this bit. By using this bit, you are telling the SPI that you want to use the SPI as controller mode.<\/span> <\/span><\/p>\n

\"Figure
Figure 4. MSTR bit<\/span><\/figcaption><\/figure>\n

REG_SET_BIT(pSPI->CR1, SPI_CR1_MSTR_Pos);<\/b><\/span><\/p>\n

This line sets the Master Mode bit in the CR1 register of the SPI peripheral. This sets the SPI to operate as the controller (master) in a multi-slave communication system. <\/span>This is controller mode. But, we need a half-duplex. That you can do using the BIDIMODE. <\/span><\/span><\/p>\n

REG_SET_BIT(pSPI->CR1, SPI_CR1_BIDIMODE_Pos);<\/b><\/span><\/p>\n

This line sets the Bidirectional Data mode bit in the CR1 register of the SPI peripheral. This enables the use of a single wire for both data input and output.<\/span><\/p>\n

 <\/p>\n

Data frame format (DFF):<\/b><\/span><\/p>\n

We want to use an 8-bit frame format for transmission or reception. Let’s clear this bit. <\/span><\/p>\n

\"Figure
Figure 5. DFF bit<\/span><\/figcaption><\/figure>\n

REG_CLR_BIT(pSPI->CR1, SPI_CR1_DFF_Pos);<\/strong><\/span><\/p>\n

This line clears the Data Frame Format bit in the CR1 register of the SPI peripheral. This sets the data frame size to 8 bits.<\/span><\/p>\n

 <\/p>\n

SSM: software slave management<\/b><\/span><\/p>\n

SSM bit has to be enabled. Why? Because, we have our dedicated CS line, which we will be toggling using software. So, we don’t want hardware to manage the peripherals. That’s why you must enable this. <\/span><\/p>\n

\"Figure
Figure 6. SSM, SSI, LSBFIRST bit<\/span><\/figcaption><\/figure>\n

REG_SET_BIT(pSPI->CR1, SPI_CR1_SSM_Pos);<\/b><\/span><\/p>\n

This line sets the Software Slave Management bit in the CR1 register of the SPI peripheral. This allows the master to control the slave selection manually (without using a hardware chip select line).<\/span><\/p>\n

 <\/p>\n

Internal slave select(SSI):<\/b><\/span><\/p>\n

SSI bit has an effect only when SSM bit is set. So, the value of this bit is forced onto the NSS pin and the value of the NSS pin is ignored.<\/span>
\n<\/span><\/p>\n

Don’t worry about this bits, just set this bit to high.<\/span><\/p>\n

REG_SET_BIT(pSPI->CR1, SPI_CR1_SSI_Pos);<\/b><\/span><\/p>\n

This line sets the Internal Slave Select bit in the CR1 register of the SPI peripheral. This sets the slave select line to a high level, so that the slave device is initially not selected.<\/span><\/p>\n

 <\/p>\n

LSBFIRST<\/b><\/span><\/p>\n

And after that, we want to send MSB first. So, clear this bit. It just means that, in 8-bit data, so the MSB of the 8-bit that is most significant bit of the frame will be sent on the wire first.<\/span><\/p>\n

REG_CLR_BIT(pSPI->CR1, SPI_CR1_LSBFIRST_Pos);<\/b><\/span><\/p>\n

This line clears the LSB (Least Significant Bit) first bit in the CR1 register of the SPI peripheral. This sets the transmission order of bits to be sent starting with the MSB (Most Significant Bit).<\/span><\/p>\n

 <\/p>\n

BR: Baud rate control<\/b><\/span><\/p>\n

Setting the baudrate of the SPI clock is the important part. So, this is generated by the controller.<\/span>
\n<\/span><\/p>\n

\"SPI
Figure 7. Baud rate control bit<\/span><\/figcaption><\/figure>\n

 <\/p>\n

What is a peripheral clock?<\/span><\/strong><\/p>\n

You know that, the SPI5 peripheral lies in the APB2 domain. So, we configured the APB2 bus clock as 90MHz. <\/span><\/p>\n

\"SPI
Figure 8. Setup AHB and APBx clocks(STM32F429)<\/span><\/figcaption><\/figure>\n

To achieve the maximum frequency of 45 MHz, the clock should be divided by 2 since 90 MHz divided by 2 is 45 MHz. However, according to our LCD datasheet, the speed should be less than 6 MHz. To meet this requirement, we need to further divide the clock by 16, which will give us a speed of around 5 MHz.<\/span><\/p>\n

What happens is, when you select the 011 option(Figure 7), the 90MHz will be divided by 16.  <\/span><\/p>\n

REG_SET_BIT(pSPI->CR1, 0X3U, 0X7U, SPI_CR1_BR_Pos);<\/b><\/span><\/p>\n

This line sets the SPI clock speed in the CR1 register of the SPI peripheral. It uses a bit mask to set the Baud Rate Prescaler (BR) bits to 0x03, which divides the system clock by 16. This sets the SPI clock speed to 90MHz\/16 = 5.625MHz, which gives you around 5.625 MHz.<\/span><\/p>\n

 <\/p>\n

CPOL and CPHA<\/b><\/span><\/p>\n

Now, go to the CPOL and CPHA selection. <\/span><\/p>\n

\"SPI
Figure 9. CPOL and CPHA bit<\/span><\/figcaption><\/figure>\n

Clock Polarity must be 0.  <\/span><\/p>\n

REG_CLR_BIT(pSPI->CR1, SPI_CR1_CPOL_Pos);<\/b><\/span><\/p>\n

This line clears the Clock Polarity bit in the CR1 register of the SPI peripheral. This sets the clock to idle at a low level.<\/span><\/p>\n

 <\/p>\n

And CPHA must be 0. The first clock transition is the first data capture edge. Let’s use CPHA as 0. This is also called SPI Mode 0. <\/span><\/p>\n

REG_CLR_BIT(pSPI->CR1, SPI_CR1_CPHA_Pos);<\/b><\/span><\/p>\n

This line clears the Clock Phase bit in the CR1 register of the SPI peripheral. This sets the data to be sampled on the first edge of the clock.<\/span><\/p>\n

 <\/p>\n

Let’s see whether we have any configuration items in the CR2 register.<\/span><\/p>\n

You have to select the frame format as SPI Motorola mode. Let’s do that.<\/span><\/p>\n

\"SPI
Figure 10. FRF (Frame format) bit<\/span><\/figcaption><\/figure>\n

REG_CLR_BIT(pSPI->CR2, SPI_CR2_FRF_Pos);<\/b><\/span><\/p>\n

This line clears the Frame Format bit in the CR2 register of the SPI peripheral. This sets the SPI to use the Motorola frame format, which is a standard format used by many devices.<\/span><\/p>\n

 <\/p>\n

Reference manual<\/a><\/p>\n

 <\/p>\n

FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n

Click here:<\/span> https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n

 <\/p>\n<\/div>\n

<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

  SPI peripheral configuration coding   In this article, let’s do the SPI_Init function. Here we do a microcontroller SPI configuration for controller mode. The code provided shows the initialization and configuration of the SPI (Serial Peripheral Interface) peripheral on a microcontroller, as shown in Figure 1.   To begin, we need to activate the […]<\/p>\n","protected":false},"author":1,"featured_media":14695,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"enable","ocean_disable_heading":"default","ocean_post_title":"SPI peripheral configuration coding","ocean_post_subheading":"","ocean_post_title_style":"solid-color","ocean_post_title_background_color":"#004793","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"off","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[],"class_list":["post-14685","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","entry","has-media"],"yoast_head":"\nSPI Peripheral Configuration: Initialization and Settings<\/title>\n<meta name=\"description\" content=\"Learn how to configure and initialize the SPI peripheral on a microcontroller in controller mode. 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