{"id":2064,"date":"2019-07-01T04:32:47","date_gmt":"2019-07-01T04:32:47","guid":{"rendered":"http:\/\/fastbitlab.com\/?p=2064"},"modified":"2023-08-30T14:53:50","modified_gmt":"2023-08-30T09:23:50","slug":"bus-protocols-bus-interfaces-cortex-m3-m4-prcoessor","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/bus-protocols-bus-interfaces-cortex-m3-m4-prcoessor\/","title":{"rendered":"Bus Protocols and Bus interfaces of Cortex M3\/M4 Processor"},"content":{"rendered":"
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Bus Protocols and Bus interfaces of Cortex M3\/M4 Processor<\/h2>\n
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In this Article, let\u2019s explore about the Bus protocols and bus interfaces used in the Cortex m3 \/m4 processor based MCUs.<\/p>\n

There are 2 bus protocols, which are very famous for interconnection between processor and the various Peripheral of the microcontroller.<\/p>\n

         1) The AHB Lite<\/strong><\/h3>\n

         2) APB<\/strong><\/h3>\n<\/div>\n<\/div>\n
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The AHB Lite<\/strong><\/h2>\n

The Cortex M3\/M4 processor use AHB lite as the main system bus.<\/p>\n

As you can see in this figure.<\/p>\n

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This is figure shows, what are the bus interfaces exist inside the ST microcontroller and how the peripherals are hooked up to different buses.<\/p>\n

The AHB lite stands for advanced high performance<\/strong><\/em> bus which is actually a lighter version of AMBA bus specification. The AMBA, which stands for Advanced Microcontroller Bus Architecture<\/strong><\/em> is the de \u2013 facto standard for on chip interconnections with the processor.<\/p>\n

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APB<\/strong><\/h2>\n

Then the next important bus protocol is APB, Which stands for Advanced Peripheral Bus<\/strong><\/em>.<\/p>\n

The APB bus also derived from AMBA specification, but this is optimized for minimum power and reduced interface complexity. So basically, it is much simpler then the AHB lite. It\u2019s mainly used to connect peripherals like UART, timers , serial protocols like SPI, I2C etc.., which do not need the high performance like AHB lite.<\/p>\n

Here you can see various peripherals are hooked up to APB1 and APB2 bus interfaces.<\/p>\n

There is a bridge which convert AHB lite protocol to APB protocol.<\/p>\n

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The cortex m3\/m4 provides 3 external AHB lite bus interface of 32 bit.<\/p>\n

The first one is called I-code interface, which is a 32 bit AHB lite bus interface.<\/p>\n

This is delicately used for instruction fetches and vector table fetches from the code memory region.<\/p>\n

All fetches on this bus are word aligned.<\/p>\n

So, in the case of 16 bit instruction, 2 instruction are fetched at a time.<\/p>\n

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Since, all thumb instructions are half word aligned in memory, two thumb instructions are fetched at a time.<\/p>\n

The D code interface is also based on AHB lite protocol and this is a dedicated bus which connects to the code memory for data accesses.<\/p>\n

Interesting thing about this interface is, it supports unaligned data accesses. It means, to access data over this bus, the data bytes need not to be aligned in the memory.<\/p>\n

Next we have system bus which is also 32 bit AHB lite bus. This bus also allows instruction fetch and data accesses from the memory devices such as SRAM.<\/p>\n

Various peripherals like SRAM , bus masters like USB, DMA, and high speed peripherals are connected over this bus.<\/p>\n

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To connect slower peripherals need not to use AHB lite bus,<\/p>\n

What they do is , they convert the AHB bus logic to APB bus logic using an AHB to APB bridge as shown in the above image.<\/p>\n

Using APB bus for peripherals which doesn\u2019t demand high performance of AHB bus can save a lot of power in the microcontroller design.<\/p>\n

So, in the typical microcontroller you will see there are 2 or more APB buses coming out of a bridge to connect various peripherals.<\/p>\n

Great! hope you understood about the bus interfaces of the the typical microcontroller.<\/p>\n

Please, comment below if you have any questions and please consider sharing this in your linkedin profile.<\/p>\n

Watch this video which explains in detail.<\/p>\n