{"id":2305,"date":"2019-07-11T05:30:57","date_gmt":"2019-07-11T05:30:57","guid":{"rendered":"http:\/\/fastbitlab.com\/?p=2305"},"modified":"2022-11-18T10:43:02","modified_gmt":"2022-11-18T05:13:02","slug":"enabling-disabling-gpio-peripheral-clock","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/enabling-disabling-gpio-peripheral-clock\/","title":{"rendered":"STM32 GPIO Lecture 20 : Enabling and disabling GPIO peripheral clock"},"content":{"rendered":"
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Enabling and disabling GPIO peripheral clock<\/span><\/h2>\n
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 <\/p>\n

In this article, let\u2019s understand about enabling and disabling of GPIO peripheral clocks. <\/span><\/p>\n

RCC is the engine that controls the clock for all the domains of the microcontroller. Like the AHB domain, APB domain, processor domain, memory domain, etc. So, according to the block diagram of STM32F407xx discovery, various GPIO ports are connected to the AHB1 bus.<\/span><\/p>\n

 <\/p>\n

\"Enabling
Figure1. RCC clock control register<\/figcaption><\/figure>\n

 <\/p>\n

So that in RCC_AHB1ENR, we can find that enabling and disabling bits to control the clocks for various GPIO ports.<\/span><\/p>\n

 <\/p>\n

\"GPIO
Figure2.RCC AHB1 peripheral reset register (RCC_AHB1RSTR)<\/figcaption><\/figure>\n

 <\/p>\n

In RCC_AHB1ENR, we will find the bit positions to control the clock for various GPIO ports from GPIOA to GPIOI. So, to make a corresponding bit as 1, the clock will be enabled. To make a corresponding bit is equal to 0, the clock will be disabled.<\/span><\/p>\n

 <\/p>\n

FastBit Embedded Brain Academy Courses<\/b><\/span><\/p>\n

Click here: <\/span>https:\/\/fastbitlab.com\/course1<\/a><\/span><\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Enabling and disabling GPIO peripheral clock   In this article, let\u2019s understand about enabling and disabling of GPIO peripheral clocks. RCC is the engine that controls the clock for all the domains of the microcontroller. Like the AHB domain, APB domain, processor domain, memory domain, etc. So, according to the block diagram of STM32F407xx discovery, […]<\/p>\n","protected":false},"author":1,"featured_media":2307,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ocean_post_layout":"","ocean_both_sidebars_style":"","ocean_both_sidebars_content_width":0,"ocean_both_sidebars_sidebars_width":0,"ocean_sidebar":"0","ocean_second_sidebar":"0","ocean_disable_margins":"enable","ocean_add_body_class":"","ocean_shortcode_before_top_bar":"","ocean_shortcode_after_top_bar":"","ocean_shortcode_before_header":"","ocean_shortcode_after_header":"","ocean_has_shortcode":"","ocean_shortcode_after_title":"","ocean_shortcode_before_footer_widgets":"","ocean_shortcode_after_footer_widgets":"","ocean_shortcode_before_footer_bottom":"","ocean_shortcode_after_footer_bottom":"","ocean_display_top_bar":"default","ocean_display_header":"default","ocean_header_style":"","ocean_center_header_left_menu":"0","ocean_custom_header_template":"0","ocean_custom_logo":0,"ocean_custom_retina_logo":0,"ocean_custom_logo_max_width":0,"ocean_custom_logo_tablet_max_width":0,"ocean_custom_logo_mobile_max_width":0,"ocean_custom_logo_max_height":0,"ocean_custom_logo_tablet_max_height":0,"ocean_custom_logo_mobile_max_height":0,"ocean_header_custom_menu":"0","ocean_menu_typo_font_family":"0","ocean_menu_typo_font_subset":"","ocean_menu_typo_font_size":0,"ocean_menu_typo_font_size_tablet":0,"ocean_menu_typo_font_size_mobile":0,"ocean_menu_typo_font_size_unit":"px","ocean_menu_typo_font_weight":"","ocean_menu_typo_font_weight_tablet":"","ocean_menu_typo_font_weight_mobile":"","ocean_menu_typo_transform":"","ocean_menu_typo_transform_tablet":"","ocean_menu_typo_transform_mobile":"","ocean_menu_typo_line_height":0,"ocean_menu_typo_line_height_tablet":0,"ocean_menu_typo_line_height_mobile":0,"ocean_menu_typo_line_height_unit":"","ocean_menu_typo_spacing":0,"ocean_menu_typo_spacing_tablet":0,"ocean_menu_typo_spacing_mobile":0,"ocean_menu_typo_spacing_unit":"","ocean_menu_link_color":"","ocean_menu_link_color_hover":"","ocean_menu_link_color_active":"","ocean_menu_link_background":"","ocean_menu_link_hover_background":"","ocean_menu_link_active_background":"","ocean_menu_social_links_bg":"","ocean_menu_social_hover_links_bg":"","ocean_menu_social_links_color":"","ocean_menu_social_hover_links_color":"","ocean_disable_title":"default","ocean_disable_heading":"default","ocean_post_title":"","ocean_post_subheading":"","ocean_post_title_style":"","ocean_post_title_background_color":"","ocean_post_title_background":0,"ocean_post_title_bg_image_position":"","ocean_post_title_bg_image_attachment":"","ocean_post_title_bg_image_repeat":"","ocean_post_title_bg_image_size":"","ocean_post_title_height":0,"ocean_post_title_bg_overlay":0.5,"ocean_post_title_bg_overlay_color":"","ocean_disable_breadcrumbs":"default","ocean_breadcrumbs_color":"","ocean_breadcrumbs_separator_color":"","ocean_breadcrumbs_links_color":"","ocean_breadcrumbs_links_hover_color":"","ocean_display_footer_widgets":"default","ocean_display_footer_bottom":"default","ocean_custom_footer_template":"0","ocean_post_oembed":"","ocean_post_self_hosted_media":"","ocean_post_video_embed":"","ocean_link_format":"","ocean_link_format_target":"self","ocean_quote_format":"","ocean_quote_format_link":"post","ocean_gallery_link_images":"off","ocean_gallery_id":[],"footnotes":""},"categories":[8],"tags":[20],"class_list":["post-2305","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","tag-stm32-gpio","entry","has-media"],"yoast_head":"\nSTM32 GPIO Lecture 20 : Enabling and disabling GPIO peripheral clock<\/title>\n<meta name=\"description\" content=\"In this article, let\u2019s understand about enabling and disabling of GPIO peripheral clocks. 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