{"id":4240,"date":"2020-12-15T11:33:08","date_gmt":"2020-12-15T11:33:08","guid":{"rendered":"http:\/\/fastbitlab.com\/?p=4240"},"modified":"2023-09-06T15:35:57","modified_gmt":"2023-09-06T10:05:57","slug":"i2c-rise-time-calculation","status":"publish","type":"post","link":"https:\/\/fastbitlab.com\/blog\/i2c-rise-time-calculation\/","title":{"rendered":"STM32 I2C Lecture 24: I2C rise time calculation"},"content":{"rendered":"
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I2C rise time calculation<\/span><\/h1>\n
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The TRISE timing for the I2C communication must be configured in the I2C driver by programming the TRISE register of the I2C register shown in Figure 1.<\/span><\/p>\n

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Figure 1. I2C_TRISE register.<\/span><\/figcaption><\/figure>\n

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Now let\u2019s include the TRISE calculation in I2C init. Refer to the TRISE register in Figure 1. Here only 5-bits are valid. <\/span><\/p>\n

The TRISE mentions the maximum rise time in Fm\/Sm mode (Master mode). The maximum rise time is given in the specification.<\/span><\/p>\n

These bits must be programmed with the maximum SCL rise time given in the I2C bus specification, incremented by 1. <\/span><\/span><\/p>\n

For example, consider the standard mode. The maximum allowed SCL rise time for standard mode is 1000 nanoseconds. If in the I2C_CR2 register, the value of the FREQ field is 0x08, which means the AHB1 clock or PCLK1 is 8MHz and T<\/span>PCLK1<\/span>=125ns. Add 1 to the result got by dividing the rise time by the time period of the PCLK1 and store it in the TRISE field.<\/span><\/span><\/p>\n

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In the I2C init, do the TRISE configuration as follows:<\/span><\/p>\n