Setting up main system clock code implementation part-3

STM32-LTDC, LCD-TFT, LVGL (MCU3) Lecture 19| Setting up main system clock code implementation part-3

 

Setting up main system clock code implementation part-3

 

Setup of the main system clock

Below code snippets shows the completed setting up LCD_CLK using the PLLSAI block.

/////////////////This step is only required if you are using RGB interface ////////////
//Setting up LCD_CLK using PLLSAI block
REG_SET_VAL(pRCC->PLLSAICFGR,50U,0x1FFU,RCC_PLLSAICFGR_PLLSAIN_Pos); /*PLLSAI_N*/
REG_SET_VAL(pRCC->PLLSAICFGR,0x02U,0x7U,RCC_PLLSAICFGR_PLLSAIR_Pos); /*PLLSAI_R*/
/*LCD_CLK = 6.25MHz*/
REG_SET_VAL(pRCC->DCKCFGR,0x08U,0x3U,RCC_DCKCFGR_PLLSAIDIVR_Pos); /*DIV*/
///////////////////////////////////////////////////////////////////////////////////////

Please note that you don’t have to do this step if you are not using the RGB interface. 

For our third hardware combination, which is the one with the external LCD, we are not using the RGB interface. These steps are not required.  

Here line 50, as you can see I have modified the PLLSAICFGR register, and the value of PLLSAI_N is 50. And the value of PLLSAI_R is 0x02. 

After that, I use the divider, the divider to divide the PLLLCDCLK clock. For that, I’m using the DCKCFGR register, and RCC_DCKCFGR_PLLSAIDIVR_Pos this bit position you have to touch. This is the 16-bit position in that register.

And I’m using 0x08. 50 divided by 8, which gives me LCD_CLK as 6.25MHz. That would be sufficient to drive the LCD module with the ILI9341 chip.

 

We have partially completed the setup of the main system clock. The setting up of the main system clock is not at over, because we have not turned on the PLL and we have to switch the PLL as the main system clock, so we’ll see that in the upcoming article.

 

Setup AHB and APB clocks

This is the third step.

Here we discuss this step with respect to the STM32F429 microcontroller, but you can apply it to any STM32 microcontroller. So, the concept is the same. 

Here, we are now getting the system clock as 180MHz. There are 3 buses in the microcontroller. The main bus, which is also called AHB bus, hosts many peripherals. Those are called high-speed peripherals. So, the high-speed peripherals are connected to the AHB bus. The clock of the AHB bus is called HCLK. 

Figure 2. Setup AHB and APBx clocks(STM32F429)
Figure 1. Setup AHB and APBx clocks(STM32F429)

 

There are two other peripheral buses.

  1. APB1 bus
  2. APB2 bus. 

And you have to set up the clocks for these buses as well. 

The PCLK1 is called as APB1 bus clock. PCLK2 is the APB2 bus clock.

Many peripherals are connected to the APB2 bus, and many peripherals are connected to the APB1 bus. All those peripherals will draw a clock from these clocks.

In this microcontroller, the HCLKs speed should not exceed 180MHz, and PCLK1 frequency should not cross 45MHz, and the PCLK2 frequency or bus speed should not cross 90MHz.

 

This information we get from a reference manual. So you have to check the reference manual. 

They have been mentioned here. The high-speed APB(APB2) and the low-speed APB(APB1). The maximum frequency of the AHB domain is 180 MHz. The maximum allowed frequency of the high-speed APB2 domain is 90MHz. The maximum allowed frequency of the low-speed APB1 domain is 45MHz. So, check your reference manual to see these numbers.

Figure 3. Reference manual
Figure 2. Reference manual

 

How do you slow down the clock?  

Here, SYSCLK is 180MHz, and the clocks for all these different domains are derived from the main system clock(SYSCLK). That means you have to slow down the main system clock. To slow down the main system clock they have given different dividers here, also called as prescalers.

Here, for AHB prescaler you have to set it to 1, divided by 1. Basically, there is no division, so  HCLK will be 180MHz.

Let’s say, you configure the PLL in such a way that SYSCLK is 360MHz, then you have to use this prescaler to match this HCLK to 180MHz.

Figure 4. Setup AHB and APBc clocks(STM32F429)
Figure 3. Setup AHB and APBc clocks(STM32F429)

And the clocks for the APB domains are derived from HCLK as you can see here(Figure 4). You must not let the clock exceed 45MHz in APB1. That’s why you have to use the prescaler 4 here. 180 divided by 4, which is 45. 

And in APB2 you have to use 2, that is 180 divided by 2, which is 90MHz. 

 

Our next task is, Configure all these prescaler values in the RCC register. 

Figure 5. Setup AHB and APB clocks(STM32F429)
Figure 4. Setup AHB and APB clocks(STM32F429)

And please check your MCU’s reference manual to know the maximum speed of HCLK, PCLK1, and PCLK2. 

 

Task: you have to program these values(1, 4, 2) into the prescaler fields of the RCC register. Now, let’s see which RCC register.

 

You have to check the RCC clock configuration register. Here you see, these fields are PPRE2, PPRE1, and HPRE.

So, you have to use these 3 fields. Here, you store the prescaler value for AHB, APB1, and APB2. 

Figure 6. RCC clock configuration register(RCC_CFGR)
Figure 5. RCC clock configuration register(RCC_CFGR)

 

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