I2C transfer sequence diagram for master sending data

In this article, let’s understand the master sending data to the slave. Then we can write the API in order to send data when the device is master. The transfer sequence diagram for the master transmitter is shown in Figure 1.

The transfer sequence is a generic discussion. It is almost the same for all microcontrollers and can be applied to any microcontroller. It is not exactly bound to the ST, and this is a beautiful diagram that will help to code the API. Let’s say the master wants to send the data to the slave.

In I2C, the device that initiates the data transfer becomes the master. For that, the device has to first trigger the START condition. When a device triggers the START condition, the device will automatically become a master in I2C. Once the start condition is triggered in the STM32 microcontroller, the event5 will happen.

What is Event5?

Look at the documentation in Figure 1. Event5 is SB = 1. That means there is a bit called the start bit in the status register of the I2C peripheral, and when the START condition is generated successfully, the SB in the status register becomes 1.

Before going to the address phase, the master has to wait until the SB becomes 1. The SB1 flag is cleared by reading the SR1 register followed by writing the DR register with an address. That means the EV5 will be automatically cleared whenever the master executes the address phase.

Remember that, in Figure 1, there is an important note mentioned below the sequence diagram, and it says that the EV5 and other events will stretch the SCL low until the end of the corresponding software sequence.

If the software delays or does not clear the EV5 event (SB1 event) or SB bit, then the SCL will be stretched, which means the SCL will be held at low by the I2C peripheral, and the master will enter into the wait state. Once the SB bit or EV5 is cleared, the master can go and execute the address phase.

In the address phase, 1 byte will be transmitted, where 7 bits are the address of the slave and another 1 bit is the read/write bit. Here read/write bit = 0 because the master wants to send the data. After executing the address phase, the master will receive the ACK only if the designated slave is present on the bus. If the designated slave is not present on the bus, then no one will ACK the address; therefore, the master may receive NACK in such a case.

If ACK is received, then EV6 will happen.

What is EV6?

EV6 means the ADDR flag of the status register will be 1, indicating that the master has successfully executed the address phase.

Remember that successful execution of the address phase means getting the ACK from the designated slave. If the master receives NACK, then ADDR will not be set. ADDR = 1 is the indication that the designated slave has received the request.

After clearing the EV6 or ADDR flag, another event called EV8_1 would happen in sequence.

What is EV8_1?

EV8_1 event sets the TxE flag of the status register, meaning that both shift and data register is empty. This is an indication for you to write data into the DR or data register.

Write the first data in the EV8_1 field. Writing the data into the data register clears the EV8_1 or TxE flag; once you write the data into the data register, it will be immediately copied into the shift register, which will start transmitting that data to the external world.

The data register will be empty since the data is moved to the shift register from it, and EV8 will happen immediately, indicating that the shift register is not empty because it is transmitting the data1 written to the EV8_1 field.

The EV8 can be cleared by writing the data to the DR, which means now write the data into Data1. After completion of the data1 transmission, the slave is going to ACK here. Once ACK is received, data in the Data1 field will be moved to the shift register, the transmission of Data2 begins, and again EV8 is set. The data3 is written in the Data2 field. Whenever the data is successfully sent, the ACK will be received, and the TxE will be set.

Remember that we also encountered the TxE flag in SPI communication. This flag will be there in almost all serial communication-related protocols. The TxE signifies that the data register is empty, and software is allowed to write the data into the data register without any corruption of data. In I2C, the TxE will be set only when the data is sent successfully, and ACK is received.

To terminate the data communication in I2C, wait for the EV8_2 event to occur after receiving the ACK for the transmission of the last byte of data (DataN or Nth byte of data shown in Figure 1).

Before generating a stop, wait till TxE=1 and BTF=1. BTF signifies the completion of the byte transfer. When you generate the stop condition, the TxE and BTF flags are automatically cleared by the hardware. Requesting the stop condition is the procedure to end the transfer sequence in the case of the master.

BTF:

BTF is the 3rd (bit number 2, as shown in Figure 2) bit of the I2C_SR1 register. BTF stands for Byte Transfer Finished. BTF bit will be set when the data byte transfer is succeeded. Otherwise, it will be 0.

Cases in which the BTF is set are as follows:

• It is set by the hardware automatically when the NOSTRETCH=0, here NOSTRETCH is an option used to control the clock stretching. If NOSTRETCH=0, then clock stretching is enabled. The clock stretching is always enabled by default.

For example, look at the 7th field of the I2C_CR1 register that is NOSTRETCH (Figure 3), which is zero, meaning that the clock stretching is enabled by default in the I2C peripheral.

• In transmission, when a new byte should be sent, and DR has not been written yet (TxE=1).

Observe Figure 1. After sending the last byte (DataN) and receiving the ACK, the data register will be empty since no bytes are left to write into the data register. After the transmission of all the bits, the shift register will also become empty. In this case, BTF will be set, indicating that both the data and shift registers are empty, and the clock will be stretched.

Look at Figure 1. The clock is stretched after the Nth byte transmission to avoid the underrun from happening and make the master enter into the wait state. Now the STOP condition can be safely raised at the end since the transmission of all the bytes is complete.

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