Significance of RGB interface signals
In this article, let’s understand the significance of Vsync, Hsync, the data enable signal, DOTCLK, and RGB data lines. All these signals are sent by the Host controller(that is LTDC).
RGB Interface signals
Vsync
- This is a vertical synchronization signal sent from the host display controller(LTDC) to the display module.
- This signal marks the “start(beginning) of a new frame”. That means, when this signal asserts, the display module understands that the host controller is going to send the data of the new frame.
In short, it just marks the “start of a new frame”.
Hsync
- This is a horizontal synchronization signal sent from the host display controller(LTDC) to the display module.
- This signal marks the “start of a new line of the frame”. That means, when this signal asserts, the display module understands that the host controller will send a new line of the current frame.
For example, if you take the image below, here 480×270 is one frame. When all those pixels are over, it asserts Vsync to indicate that it is going to send a new frame.
And this image contains 270 lines. That means, if you want to send this image only one time, then Vsync asserts one time and Hsync asserts 270 times. For every line, Hsync asserts.
DE (Data Enable)
- This is sent from the host controller(LTDC) and indicates whether the RGB data is valid or not.
- When DE = 0, the display module doesn’t read the RGB data because it is invalid.
- When DE = 1, the display module reads the RGB data and displays it on the panel.
DOTCLK(PCLK)
The clock signal is sent from the host controller(LTDC) to read the RGB data when DE=1; the Display module reads the RGB data during the rising edge of DOTCLK. This also indicates how fast RGB data is made available to the display module.
If the pixel clock or DOTCLK frequency is more, then you can make the display module to read the data more quickly. You can make the display module, and read the data very fast.
That doesn’t mean you can choose any value for the pixel clock(PCLK). It also depends on the capability of the display driver chip. The frequency of the PCLK or DOTCLK should be adjusted as per the capability of the display driver chip.
RGB Data lines
The host controller must support 24-bit data lines to carry RGB data. The display modules samples these data lines only when DE = 1 during rising edge of DOTCLK.
Note that the display module does not need to support 24-bit data lines to accept RGB data. You have to check the display module’s pin capability while interfacing.
As I said previously, the display module may support just 16 lines or 18 lines, they need not support 24 data lines. But, as per the MIPI DPI, the host controller must support 24-bit data lines.
Now to understand Vsync, how does it work?
You can get some information from the below image.
Here we are sending 4 frames. Before the host sends the Frame-1 data it should assert the Vsync. So, Vsync goes low.
Here, Vsync will be asserted first for some duration, that’s what we call the width of Vsync(Wvsync). And that duration (the gap) should be indicated by the datasheet of the display module driver chip.
After that assertion, the host controller should wait for some time, which is called the width of back porch (Wvbp). And after that only it should start sending the actual data.
Then here in the vertical front porch, all the pixels of the frame are over. So, the display controller must produce a small gap, which is also called the width of the vertical front porch (Wvfp). After that only it can assert the Vsync again to indicate the new frame, like that. But, Hsync asserts for every line like this.
Get the Full Course on STM32-LTDC, LCD-TFT, LVGL (MCU3) Here
FastBit Embedded Brain Academy Courses
Click here: https://fastbitlab.com/course1
