STM32 I2C Lecture 48: I2C IRQ handler implementation Part 5

  • Post author:
  • Post category:Blog

 

I2C IRQ handler implementation Part 5

 

 

In this article, let’s discuss the creation of the handle for the interrupt generated by the setting of the TXE flag.

When the TXE flag is set, that indicates that the data register is empty, and the software has to put a data byte into the data register to send that data byte to the external world.

 

Steps to be followed when the TXE flag is set:

  • When a TXE flag is set, you have to do the data transmission.
  • Before starting the data transmission, first, confirm the application’s state. The data transmission must begin only if the application state is busy in TX. Let’s check the application’s state by using the if statement, as shown in Figure 1.
I2C IRQ handler implementation Part 5
Figure 1. Code to check the application’s state.

 

  • If the application’s state is busy in TX, then start the data transmission as follows:
  • First, check whether the length value stored in the TxLen variable is greater than 0 or not (Figure 2).
I2C IRQ handler implementation Part 5
Figure 2. Code to check the value of the TxLen variable.

 

  • If the length is greater than zero, then load the data into DR (Figure 3).
I2C IRQ handler implementation Part 5
Figure 3. Code to load the data into DR.

 

  • Decrement the TxLen variable (Figure 4).
I2C IRQ handler implementation Part 5
Figure 4. Code to decrement the TxLen variable.

 

  • Increment the buffer address (Figure 5).
I2C IRQ handler implementation Part 5
Figure 5. Code to increment the buffer address.

 

Whenever the TXE is set, the control will enter into the if statement, shown in Figure 6. If the application’s state is busy in TX and the length is greater than 0, then 1 byte will be transferred to the DR.

I2C IRQ handler implementation Part 5
Figure 6. Handle for the interrupt generated by the TXE flag.

 

All the tasks in Figure 6 must be performed only when the device is master. Therefore, before performing these tasks, you should confirm whether the device is master or not. At any point in time, you can ensure the device mode by checking the MSL bit of the status register (Figure 7). If the MSL bit is set, then you can say that the device is behaving as master. Otherwise, the device will be in slave mode. This bit is set by the hardware as soon as the interface is in Master mode (SB=1) and cleared by the hardware after detecting the stop condition on the bus or loss of arbitration or when PE=0.

I2C IRQ handler implementation Part 5
Figure 7. Status register 2.

 

Now let’s check the device mode, as shown in Figure 8.

I2C IRQ handler implementation Part 5
Figure 8. Modified handle for the interrupt generated by the TXE flag.
Tags:

FastBitLab

The FastBit Embedded Brain Academy uses the power of internet to bring the online courses related to the field of embedded system programming, Real time operating system, Embedded Linux systems, etc at your finger tip with very low cost. Backed with strong experience of industry, we have produced lots of courses with the customer enrolment over 3000+ across 100+ countries.